In today's digital world, high-speed data transmission is an omnipresent necessity. As a crucial data transfer interface in modern computer systems, Peripheral Component Interconnect Express (PCIe) plays an essential role. However, despite its widespread use, many people want to know more about it. Today, KingSpec will lead us in delving into PCIe's development history.

The Era of ISA Bus

ISA bus was a bus standard created by IBM for the PC/AT computer. Due to its good compatibility, ISA was the most widely adopted system bus in the 1980s. However, its weaknesses, such as low transfer rates, high CPU usage, and the occupation of hardware interrupt resources, were also apparent. The elimination of the ISA bus became inevitable.

Emergence of PCI Bus

In June 1992, Intel invented an interface standard called Peripheral Component Interconnect, abbreviated as PCI. The characteristic of the PCI interface is that it uses parallel transmission and can achieve different data transfer speeds depending on the connection's data width and frequency. Compared to the previous generation ISA, PCI had a significant speed improvement and could automatically configure resources and support plug-and-play, quickly capturing the market amidst the competition among various manufacturers.

However, the bandwidth of PCI was limited and gradually became a bottleneck for increasingly powerful GPUs and other high-performance units. Therefore, AGP and other bus interface standards specifically for graphics cards were developed based on PCI technology. AGP still used parallel data transmission. As system performance continued to improve, the demand for bandwidth increased, and parallel transmission technologies like PCI and AGP could not bring further performance improvements given the technical conditions at the time.

The Birth and Development of PCIe

In 2001, the nonprofit organization PCI-SIG and Intel, AMD, Broadcom, IBM, Microsoft, and other companies proposed a new bus standard, PCIe.

1. Advantages of PCIe

PCIe is a high-speed serial point-to-point dual-channel high-bandwidth transmission standard. Connected devices have dedicated channel bandwidth and do not share bus bandwidth. It mainly supports active power management, error reporting, end-to-end reliable transmission, hot swapping, and Quality of Service (QOS) functions. The main advantage of PCIe is its high data transfer rate and significant development potential.

2 . PCIe Specifications

PCIe has various configurations: x1, x4, x8, x16, x32. The number after "x" represents how many lanes the PCIe slot has (how data flows in and out of the PCIe card). A PCIe x1 slot has one lane and can transfer one bit of data per cycle. A PCIe x2 slot has two lanes, transferring two bits of data per cycle, and so on. For example, Gen 3x2 and Gen 3x4 represent the third-generation PCIe standard's dual-channel and quad-channel configurations.

Most desktop computer motherboards have several PCIe slots for adding general-purpose graphics cards, various peripheral cards, wireless network cards, or solid-state drives. The type of PCIe slots available in a PC depends on the motherboard you purchase. You can insert a PCIe x1 card into a PCIe x4 or x16 slot, but it will always operate in PCIe x1 mode. Similarly, you can insert a PCIe x8 card into a PCIe x4 slot, but it will only use half the bandwidth.

4. Evolution of PCIe

1. PCIe 1.0 to PCIe 3.0 (2003-2010)

PCIe technology began in 2003, with PCIe 1.0 having a data rate of 2.5 GT/s. The PCIe 2.0 standard, released in 2006, doubled the data rate to 5.0 GT/s. The first two generations of PCIe technology used 8b/10b encoding, which resulted in a 25% encoding overhead.

In 2010, PCIe 3.0 increased the data rate to 8.0 GT/s and adopted a new 128b/130b encoding mechanism, doubling the bandwidth per pin compared to PCIe 2.0. The new encoding mechanism ensured high reliability through a fault model detecting three random bit flips and introduced several innovative methods for framing data packets at the physical layer while preserving the packet format sent from the upper layers.

The PCIe 3.0 specification also added enhanced signal instructions and optimizations for data integrity, including improvements to transmitters, receivers, and topologies, along with re-optimized PLLs and data channels. Additionally, the PCIe 3.1 standard, an updated version of PCIe 3.0, was released in November 2014, introducing several changes, including power management, performance optimizations, and feature extensions. However, the fundamental data transfer capability remained unchanged.

2. PCIe 4.0 (2017)

Following the pace from PCIe 1.0 to PCIe 3.0, PCIe 4.0 should have been released around 2014 or 2015, but PCI-SIG didn't release it until mid-2017, a delay of 2-3 years, which also postponed its application.

PCIe 4.0 took seven years to double the data rate from 8.0 GT/s to 16.0 GT/s (approximately 2GB/s per lane, or a total of 64GB/s). PCIe 4.0 retained the same 128b/130b encoding scheme, and the PCIe standard maintained backward and forward compatibility through software and mechanical interfaces. This means PCIe 3.0 cards can work on PCIe 4.0 motherboards, and PCIe 4.0 cards can work on PCIe 3.0 motherboards but are limited to the performance of the PCIe 3.0 interface.

To better understand the improvements PCIe 4.0 brings, here is a detailed comparison between PCIe 3.0 and PCIe 4.0:

3. PCIe 5.0 (2019)

The rise of technologies like cloud computing, AI, and machine learning has increased the need for faster data processing. To meet these demands, I/O bandwidth must grow rapidly. For instance, 400 Gb networks need 32.0 GT/s x16 PCIe to maintain bandwidth, prompting the swift introduction of PCIe 5.0 within two years of PCIe 4.0.

The key upgrade from PCIe 4.0 to 5.0 is speed, with the existing 128b/130b encoding from PCIe 3.0 and 4.0 allowing higher data rates. The channel loss limit increased to 36 dB, with better connectors reducing loss from higher frequencies.

PCIe 5.0 also supports alternative protocols, enabling some accelerators and smart NICs to efficiently manage data outside the PCIe protocol by mapping and caching system memory. Additionally, system memory is shifting to PCIe PHY for its high bandwidth, low latency, and energy efficiency.

PCIe 4.0 and 5.0 will coexist for a time. PCIe 5.0 is suited for high-performance needs, such as AI workloads and network applications, making it ideal for data centers and HPC environments. Meanwhile, PCIe 4.0 will continue to serve less demanding applications like desktop computing.

4. PCIe 6.0 (2022)

In January 2022, PCI-SIG officially released the final version 1.0 of the PCIe 6.0 specification. From a technical standpoint, PCIe 6.0 represents the most significant change in nearly 20 years of PCIe history.

Major Changes

• Data transfer rate doubled from 32GT/s to 64GT/s

• The encoding scheme shifted from NRZ signaling mode to PAM4 signaling mode. Unlike NRZ, which uses two voltage levels (0 or 1) to transmit 1 bit per clock cycle, PAM4 uses four signal levels, allowing each signal to represent two bits (00, 01, 10, 11). This effectively doubles the data transmission capacity but comes with a higher bit error rate (BER).

• Transition from variable-size TLP to fixed-size FLIT

 (CRC) scheme provides a robust error detection mechanism to counteract the high error rate associated with PAM4.

Future Outlook

The newly released PCIe 6.0 has yet to progress in practical applications. Currently, mainstream applications still use PCIe 3.0 and PCIe 4.0, while PCIe 5.0 has entered the promotion phase. More manufacturers are launching SSD products that support PCIe 5.0, and some new GPUs and CPUs have begun adopting PCIe 5.0. Overall, the latest generations of PCIe 5.0 and PCIe 6.0 have already emerged and are gradually being applied.